As part of the on-going Harlequin design I've been looking at what would be required to implement a ULA replacement for a standard ZX Spectrum 48K. One of the main differences in the Harlequin design is the lack of dynamic memory interface. Over the last few weeks I've carried out a detailed examination of the ULA dynamic memory interface, and produced a simple design that not only behaves in the same way as the ULA, it also suffers from the same side-effect that causes the "Snow Effect"
Thanks are due to James (http://www.jrok.com/) for painstakingly soldering little tiny wires onto the SCLD in his Timex TS2068 so that he could hook up an analyser, and for sending me various traces for that and an issue 3 ZX Spectrum. Without his help this analysis would have been extremely painful!
The ULA is responsible for generating the RAS and CAS signals for the lower 16K RAM for both itself and the Z80.
During a video read, the ULA places a row address on the bus and activates RAS. This is followed by a column address and the assertion of CAS for the first byte fetch (equivalent to Harlequin's AL1) and then the attribute column address and assertion of CAS for the second byte fetch (Harlequin's AL2). The RAS is removed halfway through this second CAS. This RAS / CAS sequence is repeated for each video byte pair fetched by the ULA. A new row address and RAS signal are generated for each byte pair, and bytes are always fetched in fours - two pairs in succession followed by a gap.
During a Z80 memory access (address range 0x4000 - 0x7FFF), the ULA generates a RAS signal in response to the MREQ, followed shortly by a CAS in response to either a RD or WR. The external multiplexers on the Z80 address bus are switched to select the column address on RAS going low. Once MREQ goes high, RAS goes high followed by CAS.
The Snow Effect occurs because the ULA contends just state T1 of an instruction fetch, and the way it cancels the contention with the rising edge of the CPU clock while MREQ is low - indicating the end of state T1. This "contention off" mode persists until the next rising edge of the CPU clock when MREQ is high, which is at the end of state T4. Now, during the refresh cycle of states T3 and T4, MREQ will go low, but this will be ignored by the ULA contention handler as it will be in its 'off' mode. However, the ULA dynamic memory RAS/CAS handler still notices MREQ going low and responds by forcing RAS low.
If an instruction fetch state T3 and T4 occur while the ULA is between fetching bytes 2 and 3, and the refresh address on the bus is between 0x4000 and 0x7FFF, then as described above, the ULA dynamic memory handler will force RAS low. Thus it cannot rise as it normally would during the second CAS assertion, but instead remains low as the next row address is placed on the bus, and into the next CAS assertion. The upshot is that the row address of the second byte pair of the four byte fetch will not get latched into the RAM.
This is the Snow Effect.
I will shortly provide screen captures of the logic analyser showing the details described above, plus a schematic of the dynamic RAM handler. This has only been tested inside a simulator - as soon as the 4116 and 4164 RAM chips I've ordered arrive I'll put it to a physical test.