The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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Let it Snow

Mar 14, 2008

With the 16K video memory replaced with 4164 dynamic memory, I hooked up the scope to take a look at the RAS and CAS signals.

The vCAS signal was not as clean as it should be - containing a regular glitch, causing the Harlequin to show a little screen noise.

Examining cause of the glitch, it turned out to be due to the propagation delay between CLK7 and HC0, introduced by the 74HC161 HC counter. The CAS design assumes that the clock signals it uses are in sync, whereas in actual fact, CLK14 and CLK7 are ahead of HCn.

The solution to this was both simple and obvious. To have CLK7 in sync with HCn we should generate them the same way. If we clock the HC counters U3-5 by CLK14, then CLK7 can be taken from U3-Q0. HC0 from U3-Q1, HC1 from U3-Q2 and so on. This will generate CLK7, which will need inverting to match the phase of the previous CLK7.

CLK14 transitions are still slightly ahead of CLK7 and HCn, and could be brought in line by passing it through a few spare gates before using it in the vRAS generation. In practise however, because we are clocking U62 and U63 D-Type flip-flops on the negative edge of CLK14, and CLK7 and HCn transit on the positive edge of CLK14, this delay has little effect. Any glitching between CLK14 and the other clocks will occur shortly after the positive edge of CLK14, and any such glitches will have ended before the negative edge of CLK14, which latches the signals into the flip-flops.

Let it Snow, Let it Snow, Let it snow...

The Spectrum Snow Effect is due to the Z80 dynamic RAM refresh cycle, as described in "Dynamic RAM and Snow". This would be blocked by the Harlequin as RFSH is considered when generating RAM16. So I disconnected this signal from the enable of the 3-to-8 line decoder U44 and tied the enable permanently high.

Next I typed in a simple test program to set the I register to 0x40 so that when the Z80 is in its refresh cycle, an address between 0x4000 and 0x407F will appear on the address bus.

 1 REM + Enable Snow +
 5 CLEAR 32760
10 POKE 32768, 243
20 POKE 32769, 62
30 POKE 32770, 64
40 POKE 32771, 237
50 POKE 32772, 71
60 POKE 32773, 251
70 POKE 32774, 201

I ran this program and it started to snow!

The display was identical to a real ZX Spectrum issue 3 I had connected to the TV at the same time, for reference. This proves that the Harlequin does indeed reproduce the ZX Spectrum timings - an excellent result as we're considering a ULA replacement.

The revised clock generation is shown in the clock and horizontal control schematics, version 1.19.

A full size (864K) photo of the Harlequin prototype, complete with DRAM can be downloaded here.