During a ULA IO port access the IO instruction must request data from or send data to the ULA when the ULA is not busy updating the display. For this to occur, state T3 of the IO instruction must complete during cycle 7 or 8 of the ULA's 8 cycle wide period.
To force T3 to execute at cycle 7 or 8 we could make it contended (with respect to memory contention during cycles 1-6) so that if were to begin at a contended cycle it would be delayed until cycle 7. However we know that T3 is not contended - T2 is, and besides, singling out T3 for contention requires more logic than T2 which is perhaps why Sinclair contend T2.
If we instead look at where T2 must execute for T3 to align with cycle 7 or 8 we find that making cycle 5 and 6 uncontended instead of 7 and 8 for IO, then T2 will either delay until cycle 5 or execute uncontended at cycle 5 or 6. This will force T3, which we know does not experience any contention, to execute at cycle 7 or 8 - when the ULA is no longer busy!
Furthermore, for (contended) floating bus access to work correctly, we require T3 to execute at cycle 5 or 6 (5 being where the last attribute byte is returned, 6 where 0xFF is returned). As all T-states are contended during a contended floating bus access, they will all execute during the two uncontended ULA cycles, so our choice is again limited to cycles 5 and 6.
Giving IO its own contention timing, uncontended during cycles 5 and 6, satisfies the ULA port requirement of T3 executing at cycle 7 or 8 and the contended floating bus requirement of T3 being allowed to execute during cycle 5 or 6.
The above is based on some thoughtful speculation as to the operation of the ULA given the observed behaviour documented in the comp.sys.sinclair FAQ, and knowledge of the Z80 IO port read/write cycles.
If the Harlequin were to implement a similar scheme, where a slightly different contention model is used for IO access, then the floating bus behaviour will be duplicated and data bus contention will be avoided. This will make it possible to implement a bulk of the Harlequin logic in a CPLD or similar, which like the ULA would only have a single bus to the outside world.