I've sorted out the required RGB levels and, as show previously, decided how the different RGB colours are to be switched to the screen. This has been drawn up in schematic videoout-1.4.pdf and uses the AL1 and AL2 control signals produced by the horizontal control circuit.
The missing component is the video memory interface.
This part of the design is straightforward, and must satisfy the following:
- Contain an address counter to step through the 6912 video memory location. This is the video address bus.
- Buffer the video address bus to the lower 16K of memory so that it may be detached when the CPU is accessing it.
- Rearrange the 'address' on the fly to switch between a display byte address and its corresponding attribute byte address.
Point 3 is interesting.
I know from my games programming in the past what is needed to convert a display byte address to an attribute byte address. The addressing scheme is a little weird, and I will have to arrange for the address bus to increment in the same way as I do in software when displaying sprites: each pixel line in sequence from the top of the screen to the bottom.
How the address lines are 'jumbled' is best shown graphically:
A0-12 are the sequential address bits and equate to the address lines from the address counter. VA0-15 is the video address bus as presented to the video memory.
Basically, for display byte addressing A5-7 and A8-10 are swapped. The same is done for attribute byte addressing, except that because attributes operate at a line level and not pixel row level, A5-7 (the pixel row number) will be ignored. To make the attribute address occupy the lower address bits, A11,12 are shifted down to VA8,9.
Mixing up the address lines in this way is easy, we just wire the address lines from the counter to the video memory but remember to swap certain lines in the process.
Because we have two different 'address patterns' to route to the memory, we can use simple 2 to 1 line multiplexers to switch between them. On input 1 of the multiplexor we wire one address pattern, and on input 2 we wire the other. Switching between input 1 and input 2 will thus switch between a display byte address and it's attribute byte address. If we also use tri-state multiplexers then we can detach the video address from the memory when the CPU is accessing it.
Address lines A0-4 and A8-10 are common to the two addresses and so can be buffered on their own.
We already have the control signals to fetch bytes from the video memory and place them on the video data bus. VASel is low when an attribute byte is to be fetched, and controls the address multiplexers. VMVen is low when access to the video memory is required - this controls the buffering. The address counter is reset at the start of a new frame by the vertical control counter reset, and the counter is clocked once both display and attribute bytes have been fetched.
A schematic showing the video address generation is shown on the schematics page (videomem-1.4.pdf).
Please note: This schematic contains a very incomplete CPU-side interface.