The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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Clock Mystery Solved

Apr 24, 2007

Lines on the screen

Whilst prototyping the display driver I discovered a faint but dark vertical line running through the top border, along the right hand edge of the main display rectangle and on through the bottom border. It is really noticeable if the border and display screen are set to the same colour.

I feared that I would never track the cause down, as I'd put it down to noise even though the prototype has been neatly laid out to try and avoid this. The only thing I had to go on was that HC8 goes high at the right hand edge of the display rectangle, and this 'noise' line may be related to that transient.

I hooked up my oscilloscope to the RGB output and noticed a dip in the signal at the time that HC8 went high. I tracked this 'dip' back to HBlank and HSync, and from there to the shared output of U9c. At this point the signal has not been inverted, so the dip is seen as a spike and very much larger in amplitude, with a duration of about 27ns.

The inputs of this AND gate are HC8 and HC>3. It appears that the transition of HC>3 from high to low lags behind HC8 going from low to high. This should have been expected due to the propagation delay of the 4 bit comparator U13 which produces HC>3.

This spike was finding its way onto VCclk and was the cause of the first test failure which I solved with a capacitor to ground. A valid fix, but in the wrong place.

The solution is to delay HC<8 so that it is in-line with HC>3. Alternatively we can filter out the spike with a low pass filter (simply a capacitor to ground). This is the method I have chosen as it saves a few logic gates, even though this would not work if we were to translate our design to a PLA or similar. In that case we would have to delay HC8 by about 30ns. At the moment, a capacitor of 200-400pf is sufficient. The original capacitor between VCclk and ground must be removed.

Alignment Issues

Another visible problem is that in about 50% of the time the prototype is switched on, I see the border continuing half a scanline more into the first line of the display rectangle, and starts again half a scanline into the last line of the display rectangle. As the left and right edges of the border are generally correct I assumed that this was a problem with the vertical counter. That and the fact that the vertical counter is counting in units of half a scanline led me to believe that the vertical counter was not starting at zero with the horizontal counter.

A quick check with the oscilloscope when the display was incorrect showed that VCrst was active when HC8 was low - which is not correct.

The fix for this is to delay VCrst going active until HCrst is active. This will synchronise even numbered half scanlines with the start of a scanline.

This simple modification gave me some practical problems in that the duration of the VCrst and HCrst signals are very very short, and due to the inevitable propagation delay and the fact that VC is generated by a ripple counter, HCrst was occurring and completing before VCrst. Here we do need to delay the signal.

To create a synchronised reset for VC we need to AND HCrst and VCrst. HCrst is active low and so is inverted, adding 10ns delay, and by adding another two inverters we achieve approximately 30ns delay before the AND. Spare NAND gates are used as inverters as they are physically close to the HCrst circuit.

I should probably test the stability of the synchronised VCrst signal over a range of temperatures to make sure the delay we have introduced is sufficient. Propagation delays should change proportionally with temperature across the whole circuit, so I don't expect this to be a problem.

New schematics available here (version 1.4).