The video circuit of the harlequin is built around a number of comparators which makes it quite flexible, and allows the timing of various signals to be adjusted. It is however complicated, particularly if you consider the internal gate-count of a comparator, something that will become important when reducing the design to a CPLD.
Because of this, I decided to have a look at the design to identify where simplifications could be made. The first candidate for investigation are the horizontal sync comparators which generate the HSync and HBlank signals.
Horizontal Blank and Sync
The horizontal HBlank and HSync signals are derived from three comparators, all comparing against the horizontal clock HC7-4.
- The first comparator defines the start of the Blank and HSync signals by detecting that the magnitude of HC7-4 is greater than 3 (0011b).
- The second comparator defines the end of the HSync signal when the magnitude of HC7-4 is greater than or equal to 6 (0110b).
- The third comparator defines the end of the HBlank signal when the magnitude of HC7-4 is greater than or equal to 10 (1010b).
The timings can be summarised as:
| HC7-4 | Cmp | HSync | HBlank |
|---|---|---|---|
| 0 0 0 0 | 0 | ||
| 0 0 0 1 | 1 | ||
| 0 0 1 0 | 2 | ||
| 0 0 1 1 | 3 | ||
| 0 1 0 0 | 4 | • | • |
| 0 1 0 1 | 5 | • | • |
| 0 1 1 0 | 6 | • | |
| 0 1 1 1 | 7 | • | |
| 1 0 0 0 | 8 | • | |
| 1 0 0 1 | 9 | • | |
| 1 0 1 0 | 10 | ||
| 1 0 1 1 | 11 | ||
| 1 1 0 0 | 12 | ||
| 1 1 0 1 | 13 | ||
| 1 1 1 0 | 14 | ||
| 1 1 1 1 | 15 |
HSync and HBlank both become enabled when HC4 is 0, disabled when HC4 is 0, and are active for an even number HC4 transitions. A little thought reveals that HC4 plays an insignificant role in defining the start and end of the signals and may be discounted, leaving just 3 bits: HC7-5.
This is confirmed when you consider the smallest unit of time that may be produced from HC7-5, given by the period of the lowest bit, HC5 = 25 x 1 / 7 MHz = 4.6us, which is exactly the period of the HSync signal. By considering HC7-5 alone we divide the scanline into 14 4.6us wide slices.
Removing the Comparators
We can use a single 3 to 8 line decoder instead of the three comparators, deriving HSync and HBlank signals from the eight decoded states:
| HC7-5 | Q | HSync | HBlank |
|---|---|---|---|
| 0 0 0 | 0 | ||
| 0 0 1 | 1 | ||
| 0 1 0 | 2 | • | • |
| 0 1 1 | 3 | • | |
| 1 0 0 | 4 | • | |
| 1 0 1 | 5 | ||
| 1 1 0 | 6 | ||
| 1 1 1 | 7 |
Our HSync signal is now being generated from a single output state of the decoder, and will therefore have a period of 4.6us. The horizontal HBlank is generated from three output states, and has a period of 3 x 4.6us = 13.7us. This is exactly the required period.
The decoder outputs are active low, and as we require an active low HBlank we could combine Q2-4 with a 3 input AND gate. Alternatively we could use an SR Flip-Flop constructed from two NAND gates, set by state Q2 and reset by state Q5. This has the advantage of eliminating the transfer of state change glitches from the decoder to the output.
The HSync signal (Q2) can be brought in line with the specification by delaying it with a D-Type flip-flop clocked by HC4. This will introduce a 2.28us delay, which is slightly over the specified 2us, but close enough, and helps to center the display on the screen.
Both the HSync and HBlank signals need to be disabled when H8 is low (as previous), and it would be convenient to use the E3 enable of the 3 to 8 line decoder to achieve this. However, as the vertical sync generator is driven by key points within the scanline, we will require the 3 to 8 line decoder to operate even when HC8 is low.
The chosen solution is to disable the HSync D-Type flip-flop by tying SET to HC8, and to force HBlank high by NANDing it with HC8.
As we have removed the horizontal comparitors, we no longer have the time-points that were used to drive the vertical sync generator. The 3 to 8 line decoder will provide equivalent signals, and as the vertical sync generator is also quite complicated the next task will be to redesign that and take into account the new decoded 4.6us scanline slices.
The redesigned horizontal sync circuit is shown in horizvideo-1.17.pdf.
Thanks to Grant Searle (http://home.micros.users.btopenworld.com) for spotting that HC4 was redundant, and suggesting the 3 to 8 line decoder alternative. You can see a photo of his Harlequin implementation at his website.