The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

< 59 of 68 >

Video Simplification - Vertical

Nov 22, 2007

Having redesigned the horizontal sync generator to remove the comparitors and reduce it's complexity, the next task is to do the same with the vertical sync generator, in particular to:

  1. Remove the comparitors
  2. Reduce the logic complexity

The first thing to do, is revisit our original VSync equations, and rewrite them in terms of the horizontal output states HQ0-7 (note that these equasions have been updated since they were described in VSync Pulses, having centered the display by adjusting HC4) :

VCclk= HC=6HC8 + HBlank
 = (HC8HC7 • HC6 • HC5HC4) + (HC8HC7 • HC6HC5HC4)
T2us= HC4
T30us= (HC8HC7 • HC6HC5 • HC4) + (HC8HC7HC6 • HC5 • HC4)

Reduction in terms of HQ

The first task is to reduce these equations in terms of the horizontal periods HQ7-0 by replacing bits HC7-5 with one of HQ7 to HQ0 as appropriate, noting that HQn is active low:

Starting with VCclk, we have:

VCclk= (HC8HC7 • HC6 • HC5HC4) + (HC8HC7 • HC6HC5HC4)
 = (HC8HQ3HC4) + (HC8HQ2HC4)

HC4 is common to both sides of the OR in the equation, and as it is the least significant term and 0, it may be ommited, giving a VCclk of:

VCclk= (HC8HQ3) + (HC8HQ2)
 = (HC8 + HQ3) + ( NOT(HC8) + HQ2)
VCclk= (HC8 + HQ3) • (HC8 + HQ2)

HC8 + HQ2 has previously been defined as the start of HBlank, so substituting HBlank gives:

VCclk= (HC8 + HQ3) • HBlank

The complete HBlank period is defined as HC8 + (HQ2 • HQ3 • HQ4), and when considered against the (HC8 + HQ3) term we see that VCclk is valid whenever HQ3 is low, regardless of the state of HC8. So we can drop HC8 from the equation giving a VCclk of:

VCclk= HQ3HBlank
VCclk= NOT (HQ3HBlank)

Next a look at T30us, remembering that HQ0-7 are active low:

T30us= (HC8HC7 • HC6HC5 • HC4) + (HC8HC7HC6 • HC5 • HC4)
 = (HC8HQ2 • HC4) + (HC8HQ1 • HC4)

Applying a bit of DeMorgan's Theorem:

T30us= NOT (HC8 + HQ2 + HC4) + NOT (HC8 + HQ1 + HC4)
T30us= (HC8 + HQ2 + HC4) • (HC8 + HQ1 + HC4)

And we can go one step further to reduce the number of inversions, and leave HC8 used in it's non-inverted form:

T30us= (HC8 + HC4 + HQ2) • ((HC8 • HC4) + HQ1)

T2us is driven directly from HC4, so there is not much to simplify!

Removing the Comparators

The two comparitors in the vertical sync circuit define which lines of the vertical sync generate 30us pulses, the other lines of the vsync contain 2us pulses. Instead of comparitors, we could use a 3 to 8 line decoder, as with the horizontal sync, however the decoder accepts only three address lines, and we will require four for VC3-0 as we have 16 states to cover, as defined by the vertical sync pulse sequence 6 x 2us, 5 x 30us, 5 x 2us.

The decoders do have active high and low enable inputs which may be used to extend the address range, as long as the address line used as the enable has a consistent state for all the desired decoder output values.

We can use the same arrangement that we used for the horizontal blank signal, that is a 3 to 8 line decoder fed into an SR flip-flop, so one decoder state will switch to the 30us pulse sequence, another will switch back to 2us pulses. The decoder will be driven from VC3-0, as were the comparators previously, but we will have to see if we can drive a decorder enable input from one of VC3-0 to get a four line decode.

As the vertical pulse sequence begins with 2us pulses, the 30us pulse selector will be off until the 7th pulse (VC3-0 = 0 1 1 0, counting from and including 0 0 0 0), where upon it will become enabled until, but not including, the 12th (1 0 1 1).

So the SR flip-flop is SET on VC3-0 = 0 1 1 0 and RESET on 1 0 1 1; therefore it be off for six half-lines, active for five half-lines, and then off for the remaining 5 half-lines, after which the sequence will repeat.

Comparing 0 1 1 0 and 1 0 1 1; we see that VC1 is high in both cases, so this can be used as the enable input, and VC3,2,0 as the address lines. Consequently, SR SET will be at state VC3,2,0 = 0 1 0 = 2, and RESET at state VC3,2,0 = 1 0 1  = 5

Cleaning up VCclk

VCclk is generated from two different sources, HBlank and HQ3, the duration of HBlank being much longer than HQ3. We previously had a problem with VCclk overlaping the time period end signal (T30us or T2us) causing irregular vsync pulses, and resolved this by passing VCclk through two D-types clocked at 7MHz. This was a bit of a hack, and not very eligent. A more attractive solution would be to process VCclk through a pulse generator (a D-type and a NAND gate) to generate a short (< 2us) pulse with which to SET an SR flip-flop, and then use the 30 or 2us period end signal to RESET it.

The period end signals need to be active low to reset the SR flip-flop, so we must invert T30us and T2us. The terms within T30us are thus ANDed instead of NANDed to give an inverted output, and HC4 (the T2us period) is NANDed with the 30us pulse selector to achieve the desired inversion.

Redefining VCrst

The pulse generated VCclk has an active low duration of half a 7MHz cycle. By carefully generating VCrst we can be sure that VCrst occurs after the VCclk at the end of a scanline. If the reset occurs at the mid-line VCclk, the screen will be shifted sidewards.

VCclk occurs with HBlank or HQ3, which equates to HQ2 or HQ3, depending on the state of HC8. We want to make sure we reset VC only when HC8 is high, which is when HBlank is active (at the end of the line). HSync is ideal as the choice of signal to synchronise VCrst with, as it occurs 2us after HBlank start (HQ2) and thus 2us after the line end VCclk pulse.

As HSync is taken from a D-Type flip-flop, we can use the inverted output (HSync) and remove an inverter from the VCrst generation.

The redesigned horizontal and vertical sync circuits are shown in schematics version 1.17.