The design implementation of the vertical sync generator basically consists of standard logic gates and a counter. There is nothing very critical (time wise) about the line counter as the VCclk frequency is very low compared to the pixel clock, so we don't need to use a synchronous counter. As I've quite a few 74HC4040 12bit ripple counters available, I decided to use one of these as it provides enough counter bits in one package for our needs.
You can download the first version of the vertical control schematic (Version 1.1) here.
Prototyping the design was quite straightforward, and I took a some of scope traces along the way.
The one signal that didn't come out quite right was the 30us pulse. This has very uneven pulse widths, but was quite regular in its unevenness. Pictures below.
This looked like the 30us end signal overlapping the beginning of the next start signal, probably due to the propagation delay in generating the 30us end signal. To overcome this I delayed the start signal by 1/7x106 seconds by passing the start signal through the spare D-Type latch clocked at 7MHz.
This seemed to do the trick:
The other traces I captured were:
30us Pulses
This picture shows the halfline start pulses along with the 30us end pulses for the long vertical sync. The pulse width has been measured as 29.7us.
2us Pulses
This picture shows the halfline start pulses along with the 2us end pulses for the short vertical sync. The pulse width has been measured as 2.30us.
Long and Short Pulse Select
This picture shows a sequence of short and long VSync pulses along with the short/long pulse selection signal.
VSync and VSyncEn
This picture shows an expanded VSync sequence and the VSyncEN vertical sync enable line.
