The ZX Spectrum Reverse Engineering and Clone Desgin Blog


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Generating the Vertical Signals

Mar 28, 2007

In addition to the VSync signals, we also need to generate a Vertical Border signal and a 'VSync active' signal, that latter so we can 'blank' the display during the vertical retrace. We're clocking VC at twice the scanline rate (VCclk) so the values in the following table have been doubled:

Row Start Row End Length Description VC9 - VC0
0 383384Video Display0 00 000 0000
384495112Bottom Border0 11 000 0000
49651116 VSyncEnable 0 11 111 0000
512623112Top Border 1 00 000 0000
6246240 VC Reset 1 00 111 0000

Three distinct groups show up in the table above:

  1. VC9
  2. VC8 • VC7
  3. VC6 • VC5 • VC4

So we can generate our control signals as:

VBorder= A + B
VSyncEn= B • C
VCrst= A • C

The last calculation we need to perform is when to generate long and short VSync pulses. Field 1 has 16 pulses in total (the sixteen half scanlines during VSyncEn): 6 short, 5 long, 5 short.

Taking VC0-3 as it counts through the 16 half scanlines, while VC0-3 > 5 and VC0-3 < 11 then we need generate long pulses, otherwise short.

We can use 4bit comparators for the > 5 and < 11 checks.

The VSync pulses themselves need to be held low for the desired time interval as we have so far only generated start and end signals, not actual pulses. This is easy to achieve with a D-Type latch which has an asynchronous reset. The start signal can clock a 1 into D, the 2us or 30us signal can then reset the latch, and taking an inverted output from the latch will give us our active low pulse of the correct width.