The vertical sync for field 1 comprises of a sequence of 6 short pre-equalising pulses, a sequence of 5 long synchronisation pulses and a sequence of 5 short post-equalising pulses.

A pulse has a duty cycle of 32us, and both types are specified as:

Pulse | Active Low (us) | High (us) |
---|---|---|

Short | 2 | 30 |

Long | 30 | 2 |

We will need two timers, one for 2us and one for 30us, to produce the correct length low pulse. At the end of a low pulse we can simply put the vertical sync line high until the start of the next pulse. We're generating one pulse per half scanline, as VC is counting half scanlines, and so we'll get the expected 32us duty cycle.

__2us Timer__

Lets consider how many HC clock cycles elapse during 2us:

2x10^{-6} x 1/7x10^{6} = 14

14 is an awkward number, so if we round to the nearest power of 2 we get 16.

16 x 1/7x10^{6} = 2.28us

Our half lines start when HC is 304 and HC is 80. 2.28us later HC will be 304 + 16 and 80 + 16. We need to see what happens to HC at a binary level during this 2.28us transition:

Decimal | Binary |
---|---|

304 | 1 0011 0000 |

319 | 1 0011 1111 |

320 | 1 0100 0000 |

80 | 0 0101 0000 |

95 | 0 0101 1111 |

96 | 0 0110 0000 |

Notice that HC_{4} goes low 16 HC clock cycles after the start of our half scanline. We have our 2us timer!

__30us Timer__

Taking the same approach, lets consider how many HC clock cycles elapse during 30us:

30x10^{-6} x 1/7x10^{6} = 210

210 again is an awkward number, so if we round to the nearest power of 2 we get 208.

208 x 1/7x10^{6} = 29.7us

So 29.7us after the start of our half scanline, HC will be (304 + 208) MOD 448 = 64 and (80 + 208) MOD 448 = 288.

Looking at this transition in binary:

Decimal | Binary |
---|---|

304 | 1 0011 0000 |

64 | 0 0100 0000 |

80 | 0 0101 0000 |

288 | 1 0010 0000 |

This transition isn't as easy to spot as the 2.28us. By inspection we see HC_{8} changes state, but HC_{4} to HC_{7} change dramatically.

I almost fell into the trap of thinking that we could look for a change to HC_{8} AND HC_{6} for the 304 to 64 transition, but thankfully I spotted that this would get confused by the half line start point 80. Instead, it would make sense to look for HC_{8} • HC_{7} • HC_{6} • HC_{5} • HC_{4}

A similar full decode of HC_{4} to HC_{8} should be carried out for HC=288, and as a lucky twist, our horizontal blank/sync start comparator is checking HC_{4} to HC_{7} against 2 (0010) which is exactly what we need.

__VSync Summary__

To generate our long and short VSync pulses we need:

- Our half-line start signals: HC=80 and HC=304
- A 2us has elapsed signal: HC
_{4}going low. - A 30us has elapsed signal: Check HC
_{4}to HC_{8}against 00100 and 10010. - A long/short pulse selector: Determined by the scanline we're on.

Now we just need to put that all together.....

At the risk of being a little dry, the following logic emerges:

VC_{clk} | = HC_{=5} • HC_{8} + HBlank |

T_{2us} | = HC_{4} |

T_{30us} | = (HC_{8} • HC_{7} • HC_{6} • HC_{5} • HC_{4}) + (HC_{=2} • HC_{8}) |

= (HC_{8} + HC_{7} + HC_{5} + HC_{4}) • HC_{6} + (HC_{=2} • HC_{8}) |