The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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Counting the lines

Mar 26, 2007

I've had a wonderfully crazy idea. What's wonderful is that it fits beautifully with the horizontal timings.

What I thought was this: If we have to generate vertical synchronisation pulses which are half a scanline in period, why don't we clock the scanline counter at twice the scanline rate so that we're counting half-scanlines instead. Then we just generate an appropriate VSync pulse for each of our 16 half-scanlines within out VSync period.

When I sat down to work out at what point within the scanline to generate the vertical clock (VC) pulses, I made a beautiful discovery:

Because we're clocking at twice the scanline frequency, we need to find two points in the scanline, equi-distant apart, at which to clock our vertical counter. As the start of the scanline for the video system is at the HSync pulse, this is obviously point number one. The second point should logically be half a scanline later.

Half a scanline is 224 pixel clock (HC) periods. The HSync begins at HC period 304, so 224 periods later is 528. Obviously HC wraps to zero when it reaches 448, so 528 MOD 448 = 80.

Looking at 80 in binary (0 0101 0000b) we discover that it is almost identical to the HSync end (1 0101 0000b). In fact, the significant portion HC4 to HC7 is exactly the same, and as we're already checking for this as the end of the HSync, this is great news!

The actual HSync only occurs when HC8 is high. When it is low we are generating display output. One of our VC clock points occurs when HC8 is high (ie the HSync) and the other when HC8 is low (as we're is in the middle of our video display period).

We need to consider HC8 when checking for HSyncEnd, as we're looking for the point at which HSyncEnd would occur if HC8 was low. Our two VC clock points are therefore (HC8 • HSyncStart) + (HC8 • HSyncEnd). It is amazing that there is such an alignment!

HSync is already generated as HC8 • HSyncStart, so we could use HSync + HC8 • HSyncEnd. However should we find it necessary to add a 2us front porch to the HSync, using HSync would affect our vertical clock timings. Instead we should use HBlank as that also begins at the very start of the scanline.