A page mode read cycle is, at 170ns, almost half that of a normal read of 320ns. If a normal read were used to fetch a display and attribute byte pair, then the sequence would take at least 3.5 T-states. Use a page mode read and the same pair takes approximately 1.25 T-states to fetch. To achieve these access rates the memory cycles would need to be performed at their absolute maximum limits, and so it comes as no surprise that the ZX Spectrum uses a page mode read and relaxes the timings a little to allow for some tolerance, fetching two bytes in 2 T-states.
Furthermore, a page mode read allows allows more time between video byte fetches for the CPU to run un-contended.
The Harlequin will also need to use page mode to fetch both the display and attribute bytes from the dynamic RAM. In this mode a single row address is presented to the dynamic RAM followed by two column addresses, one for each byte to be read. Therefore the address bus must be split into row and column addresses, such that a pair of display and attribute bytes share the same row address, but different columns.
Examining again the ZX Spectrum video address mapping:
We immediately see that the lower address bus is unchanged between display and attribute byte addresses, however the upper address bus does change. This is of course no accident.
Rows and Columns
The address mapping in the Spectrum is such that an attribute byte address does not contain the three address lines that make up the Pixel Row in Line, as the same attribute byte is to be fetched for all eight pixel rows in a character line. As these three address lines will be present in the display byte address but not the attribute byte address, they need to occur only in the column address, as it is the column address that changes between byte fetches in page mode read.
The 4116 dynamic memory used in the Spectrum has a 7-bit multiplexed address bus so in our diagram above, VA0-VA6 is the row address, VA7-VA13 the column address.
Address lines A5-A7 give the pixel row within a character line, and as we have a 7-bit RAM bus, to place them in the column address one would naturally position them at VA7-VA9. However, in the Spectrum this is not the case, and they actually occur at VA8-VA10. The reason for this is probably that by placing the pixel row address at lines VA8-VA10, it is easy for software to step to the next pixel row when displaying text by simply incrementing the high byte of the display address.
Address lines A8-A10 are consequently pushed out of the way and are shifted down to occupy the space vacated by A5-A7.
All that remains is to set up the two column addresses, one with the pixel row included and one without. Without the pixel row in the attribute address, lines A10-A12 are shifted down, and as the attribute bytes are to follow on directly after the display bytes in memory, the most significant address lines VA10 and VA13 must be set appropriately.
The address of the last pixel row byte in column 31 of line 23 is 0 1 0 1 1 1 1 1 1 1 1 1 1 1
The first attribute byte is at the very next address, i.e. 0 1 1 0 0 0 0 0 0 0 0 0 0 0
Which makes VA13-10 = 0 1 1 0
This address arrangement has already been implemented by the Harlequin, but the design behind the address organisation and it's relevance to dynamic memory access was not discussed.
Multiplexing
The row and column addressing is easy to implement in the Harlequin by multiplexing VA7-0 and VA8-13 into a 7-bit address via 2-to-1 line multiplexers. The multiplexers should select the column address shortly after the DRAM has latched the row address, by switching on RAS which has been delayed by a few gates in series.
As there are two pairs of RAS/CAS signals, one for video access and one for CPU, they need to be combined to create overall RAS and CAS:
RAS = vRAS • cRAS
CAS = vCAS • cCAS
Control Signals
Quite a few of the control signals that used to drive the static memory interface will change, or be removed. For instance we no longer require the VRD and VCS read and select signals, as their function is replaced by RAS. Read is assumed in the absence of WE, which is forced high during a video circuit access, just as previously.
The only slight timing change is the way we generate the signal which switches between the CPU address bus and the video address bus. Previously this was derived from AL1 • AL2, but there is always a visible glitch in the output as AL1 switches to AL2. Instead, we can generate a smoother bus switching signal from an SR flip-flop set on C3 and reset on C7. Another advantage of using an SR flip-flop is that it offers a Q output in addition to a Q output, both of which change state at the same time. Previously the bus select signal needed an inverter to select one bus and not the other which, due to the inverter propagation delay, would mean that both address buses were selected for 9ns or so when the video circuit took control of the memory.
The new dynamic memory interface circuit, and revised video memory circuit are shown in schematics version 1.18.