The intermittent floating bus failures and the recent discovery that sometimes after power-up the floating bus does not really work at all, leads me to suspect the CPU clock and AL1, AL2 timing.
I hooked up the oscilloscope to CLK3.5 and AL1 and immediately noticed that the clock was going high when AL1 was going low. This is incorrect and out of phase:
| T1 | T2 | T3 | T4 | T5 | T6 | T7 | T8 | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CLK3.5 | ||||||||||||||||
| AL1 | ||||||||||||||||
I toggled the power off and on and repeated the measurement. This time the clock was correctly going lown when AL1 was going low.
The control signals AL1 and AL2 etc are derived directly from CLK7. CLK3.5 is derived from CLK7 by dividing it with a D-Type flip-flop. If these two clocks do not both start at the same (low or high) state, then CLK3.5 will be out of phase with AL1 etc which appears to be happening occasionally.
The 3.5MHz clock signal is produced by clocking the input of a D-Type flip-flop wired in toggle mode with the 7MHz clock. As this flip flop opperates in toggle mode, at each positive edge of the 7Mhz clock its output will change state. We can predict the state of the next transition because we know the previous state, but at power on we do not know this.
The solution is to make sure that both the 7MHz and 3.5MHz flip-flops start at the same state by holding their Clr lines low momentarily during power up. This is identical to the technique used to reset the Z80 on power up.
Having done this CLK3.5 always shows the correct phase with respect to CLK7, and the floating bus test now consistently returns sensible bus values, even if the full test still reports a few errors - probably still due to an interrupt problem.
The modifications appear in schematics version 1.10.