The Harlequin ZX Spectrum clone is now functionally complete and timing accurate. Next in its evolution and to be discussed on this blog will be the following:
- Simplification of logic, where possible.
- Identification of timing critical sections, and potential redesigns to improve stability (see below regarding HCT chip family).
- CPLD/FLGA design. In discrete logic the Harlequin is quite large so a CPLD version will be required if any sort of production kit is to be produced.
- PCB design - probably practical only for the CPLD version.
- A look at enhanced video modes and NTSC (moving to TS2068 support).
- Dynamic memory support (allowing for ULA replacement in a real Spectrum and 128K support).
- 128K support, and potentially Spectrum SE support.
- ULA internals documentation.
The HCT Family
Grant Searle (http://home.micros.users.btopenworld.com) has been busy building a Harlequin Clone of his own, and has chosen to use the HCT family of chips. This has highlighted some timing sensitive areas of the Harlequin design (which uses the HC family), and several minor adjustments need to be made to correct these issues.
Once a full understanding of the cause and effects of these issues has been gained, I will document them on this blog, along with potential re-designs or, at the least, mandatory modifications to the original prototype when using different logic families.