We identified in video parameters that the pixel clock is 7MHz, and is therefore the clock rate of our shift register. We will need to keep track of which bit is being shifted out of the register in order to reload it at an appropriate time. This should be quite easy to achieve by using a horizontal counter to count through the 448 pixel clock cycles per row and taking modulus 8 of this. We'll call this counter HC.
The attribute and screen byte memory read can be synchronised to the horizontal count MOD 8, and the horizontal count itself can be used to determine when we're in the screen or border area or during the horizontal flyback.
The diagram above shows the horizontal video counter MOD 8 (0..7) and three derived control signals: the latch enable signals AL1, AL2 and a memory fetch selector VAsel.
VAsel goes low to select an attribute byte address, high to select a screen byte address. AL1 goes high-low-high to latch the attribute byte into the latch, AL2 goes high-low-high to latch the screen byte into the shift register. An assumption has been made that the latch and shift register will latch the data on a low to high transition of the latch signal. Thus data will be latched into the shift register at precisely the start of pixel cycle 0.
These signals will help us collect the bytes to be transferred to the screen, what is missing of course is some sort of video address clock and properly timed horizontal video synchronisation signals.
Creating an address clock/counter is easy. The ZX Spectrum screen memory starts at 4000h and ends at 57ffh and is therefore page aligned (i.e. its least significant byte is zero). We can arrange a counter to start at zero and be incremented every time a byte is read from memory (probably by latch enable signal AL2). This counter will need to be reset once we've completed a single video frame.
Creating correctly timed video synchronisation signals is a little more tricky, and since we're on the subject of timing and video signals we're probably best looking at this first, before the video address creation.