The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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Centring The Display

Apr 08, 2007

I hooked up my real ZX Spectrum to the TV and with a bit of masking tape, marked out the four sides of its display rectangle on the glass. The Harlequin in comparison is a good one third border width further to the right, and looks uncomfortable there!

Even though there are an equal number of border 'pixels' in the left and right border, the time we've allowed between the right and left border for the horizontal flyback (96 Horizontal Clock cycles) must be longer than necessary. As the horizontal sync pulse is at the start of this period, it is in effect too early, leaving too much time before the start of the left border.

If we want to adjust the display rectangle left or right, we will need to change the timing of the horizontal sync.

Luckily adjusting the timing of the horizontal sync and blanking signal is easy as they're generated by three binary comparators connected to the horizontal counter (HC).

These 4bit comparators are connected to counter lines HC4-7, and so the smallest adjustment we could make would be by a factor of 16. Each HC clock pulse equates to 1 pixel, so our smallest margin of adjustment is by 16 pixels.

To move the display rectangle left we delay the start of the blanking/horizontal sync period effectively making the right hand border wider and the left hand border narrower. We do this by adding 16 (because our least significant comparator bit is HC4):

HC Start HC End Length Description
0255 256Video
25631964Right Border
41644732Left Border

Notice that we've maintained the width of the blanking period, as this is part of the PAL specification.

Making this adjustment means that we've changed the timing of the scanline start, which we've previously defined as being the start of the blanking period. This will also have caused our scanline midpoint to move, so for the vertical sync pulses to be accurate we will need to adjust these times as well.

Fortunately both the scanline start and midpoints are derived from the same comparators that define the HSync start and end times, so altering the horizontal timings will also alter the vertical sync timings!

The only minor adjustment that needs to be made to the vertical sync timing is the sync-pulse end point - these are currently determined by checking specific HC bits. As we've delayed our timings by 16 HC cycles, we will find that where we were looking for HC4 we should now be looking for HC4 and vice versa.

This can easily be accomplished by inverting HC4 before checking HC4-8 for the vertical sync endpoints.

The updated horizontal control schematic (version 1.2) and the updated vertical control schematic (version 1.3) can be downloaded from the schematic download page