The ZX Spectrum Reverse Engineering and Clone Desgin Blog

Harlequin

A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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The ZX Spectrum Dynamic Memory Control

Jan 12, 2008

Over the last month or so, I've been carrying out a detailed analysis of the Spectrum dynamic memory interface from the traces provided by James (http://www.jrok.com/). The timing of the signals shown in the traces vary a little due to the analyser being set to TTL levels, causing the edges to be quantised sharply to the TTL trigger point. CPU_CLK is the output from the ULA, Z80_CLK is taken at the Z80 CPU.

First a note about dynamic memory which is the type employed in the ZX Spectrum. Dynamic memory has its address bus divided in two, with the lower address lines selecting the memory location row and the upper address lines selecting the memory location column. In order to reduce the number of pins required for the dynamic memory chip, the lower address lines and the upper address lines share the same pins. Because of this, there are two address latch signals: Row Address Strobe (RAS) and Column Address Strobe (CAS). To access a memory location within the dynamic memory, the row address is placed on the half-size bus and RAS activated, then the column address is placed on the half-size bus and CAS activated.

There are two separately occasions when the ULA generates RAS and CAS signals: once for ULA video access to the lower 16K, and the other when the CPU requires access.

ULA Video Access

When the ULA is updating the display and needs to access the lower 16K of memory it generates a RAS and CAS sequence synchronised with its display byte fetch.

If we look at the video access RAS and CAS sequence, we see that the dynamic memory is being accessed in paged mode (multiple column locations are accessed within a single row). If we refer to the ZX Spectrum's memory arrangement we can see why: the display byte and its corresponding attribute are stored in different columns of the same row (i.e. the lower addres lines (row address) are the same for the display byte and its attribute byte). When the address changes to access the attribute byte, it is only the column address that needs to change.


ULA Video Access (Click to enlarge.)

The ULA signal generation sequence is this:

  1. The row address of the display/attribute byte pair is placed on the bus (maddr 0x00).
  2. One CLK7 cycle later, at the rising edge of MCLK (CLK14), RAS goes low (72ns).
  3. Straight after RAS goes low, the display-byte column address is placed on the bus (maddr 0x00)
  4. At the next falling edge of CLK14, CAS goes low (36ns).
  5. CAS remains low for slightly less than three complete CLK14 periods, going high with the third falling edge of CLK14.
  6. At the rising edge of CLK14, the attribute-byte column address is placed on the bus (maddr 0x30).
  7. At the next falling edge of CLK14, CAS goes low.
  8. During this second CAS, RAS goes high, having been low for six CLK14 periods.
  9. CAS remains low for three complete CLK14 periods, going high with the third falling edge of CLK14.
  10. Shortly before CAS goes high, the next display/attribute byte row address is placed on the bus (maddr 0x01)
  11. RAS goes low on the next rising edge of CLK14 and the sequence 3..9 repeats once more.

A number of the control signal transitions are not aligned with the master clock (CLK14) edges. A proportion of this propagation delay will be intentional, allowing safe margins within which the 4116 dynamic memory can operate.

The Harlequin generates addresses and other signals at slightly different points within the fetch cycle, so the ZX Spectrum RAS and CAS timings would not work as they are. However, the same signal sequence must be used to maintain correct floating bus behaviour, so the timings need to be adjusted relative to AL1 and AL2.