The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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Horizontal Control Schematic

Mar 19, 2007

I've put the designs outlined in the last few sections into a schematic, and have started building it to test the timings. I'll upload photos and scope pictures when I have them (23 Mar 2007: pictures here).

The heart of the horizontal timing generator is the 448 step pixel clock counter. Using a counter such as the 74HC4040 would not be wise due the the ripple effect seen at it's output as it clocks through each step. Something like the 74HC161 or 74HC163 are a good choice. The 74HC163 has a synchronous reset which eliminates reset glitches at the output by synchronising the reset with the next clock transition. However this would greatly complicate the reset circuit (back to zero) as we would have to detect the counter at state 447 in order to assert the reset line for the next clock transition (447 is 110111111 binary).

If we don't mind a tiny glitch at reset then we can use the 74HC161 asynchronous reset device, detecting when 448 is reached (111000000) and resetting the counters immediately. The reset glitch seen is HC0 staying low momentarily longer than usual and HC6 to HC8 being unusually high together whilst the reset line is asserted, but these will have a neglegible effect.

The repeating 8 states from which AL1, AL2 etc are generated can be produced using a 3 to 8 line decoder such as the 74HC138. A small amount of discreate logic implements the timing graphs shown earlier.

The simplest way of detecting when our horizontal counter reaches the key points on our horizontal row is to use comparators such as 74HC85. We have already simplified the counter lines that need to be considered to 4, so these devices work well.

Finally, delaying HC8 to to generate Vout/HBorder/PIXen can be done either through a shift register or through a few cascaded D-type flip-flops. I decided to use an octal D-Type latch clocked by the pixel clock for this, using the first two D-Types in series. This leaves the other 6 D-Types available to delay other signals later, should that be required.

It is worth noting that although a number of control signals are produced, we may find that some are not used in final design. For instance I realised whilst drawing up the schematic that the delayed HC8 signal (PIXen or ~Vout/HBorder) combined with VBorder to produce the overall screen Border signal may be redundant. We already generare HC8 OR VBorder in producing ~VMven, so we could delay that OR to generate ~Vout/Border instead. This would save an additional gate at the loss of signal HBorder.

A note to this effect has been made on the schematic for reference.

Download the schematic as a PDF here.