The ZX Spectrum Reverse Engineering and Clone Desgin Blog


A site dedicated to the reverse engineering of the ZX Spectrum and related projects.

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Alignment Issues Again

May 9, 2007

I started thinking about the interrupt timing today, and that I'd have to generate it so that 14336 T-States after the Z80 acknowledges it, the first display byte is being sent to the TV. We know that the interrupt is generated during the vertical sync of the display, and 64 scanlines later the first display row is being output (one scanline = 224 T-states, 64 x 224 = 14336). See Vertical Control for details.

The horizontal counter defines HC=0 as being the start of the display rectangle and not the start of the left hand border, so our interrupt must be generated at this point, 64 lines before the first display rectangle scanline, which is the first scanline of the vertical sync.

That's when I realised that I'd made a mistake in my correction to the vertical counter reset to solve the intermittent alignment problem.

The vertical counter counts half-scanlines, and when I was looking at the alignment problem I mistakenly considered the start of the first half scanline to be at HC = 0, which was why I introduced HCrst as the solution. This is of course not the case, and the solution though seeming to work would have missaligned HSync and VSync.

The true solution is to make sure that VCrst is generated at the start of the first half-scanline by waiting for that half-lines start pulse: HBlank - one of the two used to clock VC. This ensures that if the VC counter starts up missaligned with respect to HC, VCrst will be delayed to reset VC to 0 at the start of a scanline and realign HSync and VSync.

This also means that the delay introduced to HCrst in generating VCrst is not required.